\chapter {Conclusions and future works}\label{conclusions}
\markboth {Chapter \ref{conclusions}. Conclusions and future works}{}

%Once you eliminate the impossible, whatever remains, no matter how improbable, must be the truth.
% Sherlock Holmes (by Sir Arthur Conan Doyle, 1859-1930)
\begin{flushright}
\sl
The opposite of a correct statement is a false statement. The opposite of a profound truth may well be another profound truth.
\end{flushright}

\begin{flushright}
\sl
Niels Bohr 
\end{flushright}
\par\vfill\par


%Comment about obtained results and proposed future works
In this thesis, a new methodology for the high level synthesis problem has been presented. It combines an high-level synthesis flow that is able to translate a behavioral specification to an RTL design and a genetic algorithm that is able to perform the design space exploration. The resulting design respects the behaviour of the original specification and it can be directly synthetised on FPGA devices. The flow has been constructed in a modular way, so new algorithms, used to solve the different sub-tasks of the high-level synthesis problem with better results, can be easily integrated, provided they fill the data structures used as interfaces in the same way.

A method for design space exploration has been also provided to reduce area due to interconnection elements. In fact, the evaluation shows that much of the area of the final design is due to these elements. Such optimization can be obtained with a proper binding of operations on the functional units. Since evaluations of the solutions can be obtained only at the end of the flow, an evolutionary algorithm has been implemented to perform multi-objective design space search. Performance and area occupation are the objectives to be optimized.

The proposed approach adopts the NSGA-II algorithm in order to find Pareto-optimal results in terms of execution latency while constraining the area of the target FPGA design. In order to evaluate each generated solution without performing complete and low level synthesis an area estimation model has been integrated. It has been shown that this model is a good estimator for real area occupation on the target devices. In fact the average error is less than 5\% and maximum error is less than 10\%. 

The flow has been applied to different benchmarks and the results demostrate that the algorithm is able to find a set of Pareto-points that reduces the requested area of about the 20\% with respect to the traditional flow.
The JPEG compression algorithm has been used as a real case study to test this flow on a real problem. The results also show that, given an area constraint, the tool is able to find a best-fit solution for the target device while examining the design space for two different functions at the same time. 

However, the resulting flow present some limitations:
\begin{itemize}
 \item the high-level synthesis flow is not able to support behavioral specification that contains loops constructs. This is due to the difficult to optimize the final design in situations where operations could be or could not be executed. Ensuring that these operations will always have a functional unit that could execute them will result in a waste use of functional units that, when the loop will not be executed anymore, will be inactive. At opposite, optimization based on control flow, are difficult to be implemented in a complete design flow, with respect to all the other optimizations that have been proposed.
\item the area model proposed presents a noise that needs to be reduced as much as possible to produce better estimations and to better aid the genetic algorithm to explore the design space;
\item memory access and hierachical design, based on the principle of the component reuse, are not supported up to now;
\item the execution time of the high-level synthesis flow increases when the complexity increases. Since a synthesis flow is performed at each fitness evaluation, the execution time of the design space exploration can become inacceptable.
\end{itemize}

To support memory access, the methodology has to support the possibility that operations can take an indefined execution time. The problem is similar to the introduction of support for loops. In fact, also in this situation an operation, in a control step, could be or could be not executed. If it is not executed, the functional unit could be also used for another operation and the overall request of modules can be reduced.

Since fitness evaluation can take a long time when the complexity of the circuit to be created increases, a surrogate of the real fitness evaluation can be used, based on theory of the estimation of distribution algorithms~\cite{sastry2006} (EDAs).

The area model used for estimation should be optimized and parameter values have to be related to the particular device or RTL synthesis tool. In fact, the RTL synthesis tools can perform synthesis in different ways and, even if the same synthesis tool is used, different results could be obtained if different target devices are used. In fact, the synthesis performed by the tool depends also on the technology of the target device and, in certain situations, different technologies can lead the tool to perform different synthesis.

Another important future work is the integration of this flow in a reconfigurable design
framework. Reconfigurable designs have strict requirements on area constraints.
The reconfigurable area is, in fact, targeted to the biggest module it has to allocate. As such, this flow would allow not only to find an optimal solution in terms of execution latency fixed the reconfigurable area for a single module, but it would make possible to find the best solutions for all the modules that will share that area.
